Loop recreation for thread-level speculation

被引:0
作者
Gao, Lin [1 ]
Li, Lian [1 ]
Xue, Jingling [1 ]
Ngai, Tin-Fook [2 ]
机构
[1] Univ New S Wales, Sydney, NSW 2052, Australia
[2] Intel, Microprocessor Technol Lab, Santa Clara, CA USA
来源
2007 INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS, VOLS 1 AND 2 | 2007年
关键词
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
For some sequential loops, existing techniques that form speculative threads only at their loop boundaries do not adequately expose the speculative parallelism inherent in them. This is because some inter-iteration dependences, which translate into inter-thread dependences at run time, are too costly to synchronize or speculate. This paper presents a novel compiler technique, called loop recreation, to transform a loop into a prologue, a kernel loop - formed with instructions from two adjacent iterations, and an epilogue so that the inter-iteration dependences in the kernel are less costly to enforce at run time than those in the original loop. We prove the concept by giving an algorithm for finding an optimal loop recreation with respect to a simple misspeculation cost model and by demonstrating performance advantages of loop recreation over two recent techniques for speculative multi-core systems running four irregular applications with indirect array accesses.
引用
收藏
页码:337 / +
页数:2
相关论文
共 50 条
[31]   Thread-level Value Speculation for Image-processing Applications [J].
Wu, Jun-Si ;
Sheiue, Yuan-Fu ;
Chen, Peng-Sheng .
2015 44TH INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING WORKSHOPS, 2015, :74-80
[32]   Adaptive Fork-Heuristics for Software Thread-Level Speculation [J].
Cao, Zhen ;
Verbrugge, Clark .
PARALLEL PROCESSING AND APPLIED MATHEMATICS (PPAM 2013), PT I, 2014, 8384 :523-533
[33]   Evaluating and Improving Thread-Level Speculation in Hardware Transactional Memories [J].
Salamanca, Juan ;
Amaral, Jose Nelson ;
Araujo, Guido .
2016 IEEE 30TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM (IPDPS 2016), 2016, :586-595
[34]   Min-cut program decomposition for thread-level speculation [J].
Johnson, TA ;
Eigenmann, R ;
Vijaykumar, TN .
ACM SIGPLAN NOTICES, 2004, 39 (06) :59-70
[35]   Tradeoffs in buffering memory state for thread-level speculation in multiprocessors [J].
Garzarán, MJ ;
Prvulovic, M ;
Llaberiá, JM ;
Viñals, V ;
Rauchwerger, L ;
Torrellas, J .
NINTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS, 2003, :191-202
[36]   Performance Comparison of Speculative Taskloop and OpenMP-for-Loop Thread-Level Speculation on Hardware Transactional Memory [J].
Salamanca, Juan .
2022 21ST INTERNATIONAL SYMPOSIUM ON PARALLEL AND DISTRIBUTED COMPUTING (ISPDC 2022), 2022, :83-90
[37]   Dynamic Core Allocation for Energy-Efficient Thread-Level Speculation [J].
Li, Meirong ;
Zhao, Yinliang ;
Si, Yongqiang .
2014 IEEE 17TH INTERNATIONAL CONFERENCE ON COMPUTATIONAL SCIENCE AND ENGINEERING (CSE), 2014, :682-689
[38]   Thread-Level Speculation on Off-the-Shelf Hardware Transactional Memory [J].
Odaira, Rei ;
Nakaike, Takuya .
2014 IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION (IISWC), 2014, :212-221
[39]   Selective restart of threads for efficient thread-level speculation on multicore architecture [J].
Lee, Sungjae ;
Lee, Inhwan .
IEICE ELECTRONICS EXPRESS, 2012, 9 (04) :290-295
[40]   The potential for using thread-level data speculation to facilitate automatic parallelization [J].
Steffan, JG ;
Mowry, TC .
1998 FOURTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS, 1998, :2-13