Circuit-Level Layout-Aware Single-Event Sensitive-Area Analysis of 40-nm Bulk CMOS Flip-Flops Using Compact Modeling

被引：23

作者：

Kauppila, Jeffrey S. ^{[1
]}

Haeffner, Timothy D. ^{[1
]}

Ball, Dennis R. ^{[1
]}

Kauppila, Amy V. ^{[2
]}

Loveless, T. Daniel ^{[1
]}

Jagannathan, Srikanth ^{[2
]}

Sternberg, Andrew L. ^{[1
]}

Bhuva, Bharat L. ^{[2
]}

Massengill, Lloyd W. ^{[2
]}

机构：

[1] Vanderbilt Univ, ISDE, Nashville, TN 37212 USA

[2] Vanderbilt Univ, Dept Elect Engn & Comp Sci, Nashville, TN 37212 USA

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2011年 / 58卷 / 06期

关键词：

Charge sharing; circuit modeling; circuit simulation; CMOS integrated circuits; compact models; flip-flops; latches; radiation effects; single-event upset (SEU); SPICE; FLIP/FLOP DESIGNS; UPSETS;

D O I：

10.1109/TNS.2011.2172692

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A circuit-level layout-aware single-event simulation capability is presented. Multiple 40-nm bulk CMOS flip-flops are analyzed to determine single-event upset (SEU) sensitive area. Comparisons between simulation results and broadbeam heavy-ion test data show excellent agreement. Simulations of single-event strikes over the entire flip-flop layout can be performed in less than 1 h.

引用

页码：2680 / 2686

页数：7

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