Access-mode predictions for low-power cache design

被引:28
作者
Zhu, ZC [1 ]
Zhang, XD [1 ]
机构
[1] Coll William & Mary, Dept Comp Sci, Williamsburg, VA 23187 USA
基金
美国国家科学基金会;
关键词
Computer simulation - Computer workstations - Energy conservation - Integrated circuit layout - Microprocessor chips - Random access storage - Shift registers;
D O I
10.1109/MM.2002.997880
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
An access-mode prediction technique based on cache hit and miss speculation for cache design is presented. With this methid, cache accesses can be adaptively switched between the way-prediction and the phased accessing modes.
引用
收藏
页码:58 / 71
页数:14
相关论文
共 19 条
[1]  
ALBONESI DH, 1999, P 32 ANN ACM IEEE IN, P238
[2]  
[Anonymous], P 8 ANN S COMP ARCH
[3]  
[Anonymous], P IEEE INT S LOW POW
[4]   Power-aware microarchitecture:: Design and modeling challenges for next-generation microprocessors [J].
Brooks, DM ;
Bose, P ;
Schuster, SE ;
Jacobson, H ;
Kudva, PN ;
Buyuktosunoglu, A ;
Wellman, JD ;
Zyuban, V ;
Gupta, M ;
Cook, PW .
IEEE MICRO, 2000, 20 (06) :26-44
[5]  
BURGER DC, 1997, CSTR19971342 U WISC
[6]   SH3 - HIGH CODE DENSITY, LOW-POWER [J].
HASEGAWA, A ;
KAWASAKAI, I ;
YAMADA, K ;
YOSHIOKA, S ;
KAWASAKI, S ;
BISWAS, P .
IEEE MICRO, 1995, 15 (06) :11-19
[7]   L1 data cache decomposition for energy efficiency [J].
Huang, M ;
Renau, J ;
Yoo, SM ;
Torrellas, J .
ISLPED'01: PROCEEDINGS OF THE 2001 INTERNATIONAL SYMPOSIUM ON LOWPOWER ELECTRONICS AND DESIGN, 2001, :10-15
[8]  
Inoue K., 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477), P273, DOI 10.1109/LPE.1999.799456
[9]  
Kim H. S., 2000, Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era, P53, DOI 10.1109/IWV.2000.844530
[10]  
MCFARLING S, 1993, TN36 DIG EQ CORP W R