CMOS high-resolution all-digital phase-locked loop

被引：0
|
作者：
Mokhtari, E [1 ]
Sawan, M [1 ]
机构：
[1] PoySTIM Neurotechnol Lab, Dept Elect Engn, Montreal, PQ H3C 3A7, Canada
来源：
Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems, Vols 1-3 | 2003年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The core of an all-digital phase locked-loop (ADPLL) is composed of a high resolution digital controlled oscillator (DCO) circuit operating in a wide frequency range, a phase-frequency detector (PFD) and an up/down binary counter. The ADPLL can be reused in many system-on-chip (SoC) applications by a proper setting of the DCO and the PFD. Extensive simulation were carried on using models of a standard 0.18 mu m CMOS technology, with a power supply of 1.8 Volts. The simulation results show that the ADPLL can operate from 26MHz to 588MHz.
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页码：221 / 224
页数：4
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