FPGA implementation of downlink DBF calibration

被引：0
作者：
Wang, Zhiguo [1 ]
Jin, Ronghong [1 ]
Geng, Junping [1 ]
Fan, Yu [1 ]
Lian, Chengdong [1 ]
Chen, Junjie [1 ]
Yang, Guomin [1 ]
Wu, Qi [1 ]
机构：
[1] Shanghai Jiao Tong Univ, Dept Elect Engn, Shanghai 200030, Peoples R China
来源：
2005 ASIA-PACIFIC MICROWAVE CONFERENCE PROCEEDINGS, VOLS 1-5 | 2005年
关键词：
FPGA; parallel orthogonal codes; VHDL; calibration; DBF;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The calibration system is very important in solving the amplitude and phase imbalance of the digital beam forming (DBF) antennas. In this paper, a hardware calibration system based on field programmable gate array (FPGA) is designed. The calibration algorithm adopted in this design is based on the parallel orthogonal codes. To improve the calibration speed, parallel design methods are used. The simulation result shows that this system can satisfy the request of the real time calibration of the downlink digital beam forming.
引用
收藏
页码：1931 / 1933
页数：3
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