FPGA implementation of downlink DBF calibration

被引：0

作者：

Wang, Zhiguo ^{[1
]}

Jin, Ronghong ^{[1
]}

Geng, Junping ^{[1
]}

Fan, Yu ^{[1
]}

Lian, Chengdong ^{[1
]}

Chen, Junjie ^{[1
]}

Yang, Guomin ^{[1
]}

Wu, Qi ^{[1
]}

机构：

[1] Shanghai Jiao Tong Univ, Dept Elect Engn, Shanghai 200030, Peoples R China

来源：

2005 ASIA-PACIFIC MICROWAVE CONFERENCE PROCEEDINGS, VOLS 1-5 | 2005年

关键词：

FPGA; parallel orthogonal codes; VHDL; calibration; DBF;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The calibration system is very important in solving the amplitude and phase imbalance of the digital beam forming (DBF) antennas. In this paper, a hardware calibration system based on field programmable gate array (FPGA) is designed. The calibration algorithm adopted in this design is based on the parallel orthogonal codes. To improve the calibration speed, parallel design methods are used. The simulation result shows that this system can satisfy the request of the real time calibration of the downlink digital beam forming.

引用

页码：1931 / 1933

页数：3

共 50 条

[1] DESIGN AND IMPLEMENTATION OF LINEAR PRECODING LTE DOWNLINK BASED ON FPGA
Chaeriyah, Nur
Astuti, Rina Pudji
Darlis, Denny
2013 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATION, NETWORKS AND SATELLITE (COMNETSAT), 2013, : 50 - 54
[2] FPGA and ASIC implementation of reliable and effective architecture for a LTE downlink transmitter
Wang, Zhou
Wu, Bin
Ye, Tianchun
IEICE ELECTRONICS EXPRESS, 2018, 15 (20):
[3] Self-calibration algorithm and FPGA implementation for data acquisition
Zhang, Gui-Qing
Zhang, Tian-Xu
Yan, Lu-Xin
Zhu, Lei
2007 IEEE INTERNATIONAL CONFERENCE ON CONTROL AND AUTOMATION, VOLS 1-7, 2007, : 658 - +
[4] An External Calibration Scheme for DBF Antenna Arrays
Pawlak, Holger
Jacob, Arne F.
IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION, 2010, 58 (01) : 59 - 67
[5] Implementation and integration of a systematic DBPM calibration with PLL frequency synthesis and FPGA
孙旭东
冷用斌
Nuclear Science and Techniques, 2014, 25 (02) : 59 - 64
[6] Implementation and integration of a systematic DBPM calibration with PLL frequency synthesis and FPGA
Sun Xu-Dong
Leng Yong-Bin
NUCLEAR SCIENCE AND TECHNIQUES, 2014, 25 (02)
[7] Implementation of RISC processor on FPGA
Mane, Pravin S.
Gupta, Indra
Vasantha, M. K.
2006 IEEE INTERNATIONAL CONFERENCE ON INDUSTRIAL TECHNOLOGY, VOLS 1-6, 2006, : 1462 - +
[8] Implementation of PRINCE Algorithm in FPGA
Abbas, Yasir Amer
Jidin, Razali
Jamil, Norziana
Z'aba, Muhammad Reza
Rusli, Mohd Ezanee
Tariq, Baraa
PROCEEDINGS OF THE 2014 6TH INTERNATIONAL CONFERENCE ON INFORMATION TECHNOLOGY AND MULTIMEDIA (ICIM), 2014, : 1 - 4
[9] FPGA Implementation of SVPWM Approximation
Boukaka, Salim
Massicotte, Daniel
Sicard, Pierre
2015 CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS), 2015,
[10] FPGA implementation of the "pyramids" block cipher
AlKalbany, A
Al Hassan, HA
Saeb, M
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2005, : 271 - 275

← 1 2 3 4 5 →