Investigation of dopingless transistor with field plates for analog and digital applications

被引：3

作者：

Zafar, Samreen ^{[1
]}

Raushan, Adil ^{[1
]}

Siddiqui, M. Jawaid ^{[1
]}

机构：

[1] AMU, ZHCET, Dept Elect Engn, Aligarh, Uttar Pradesh, India

来源：

MICROELECTRONICS JOURNAL | 2022年 / 128卷

关键词：

Field plates; Electrostatic doping; Off-state tun-neling; Gate induced drain leakage (GIDL); Lateral band to band tunneling (L-BTBT); Parsaitic BJT; JUNCTIONLESS TRANSISTOR; DUAL-MATERIAL; LOW-POWER; DEVICE; DESIGN; SPACER; FETS;

D O I：

10.1016/j.mejo.2022.105546

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work demonstrates the influence of introducing field plates to an electrostatically doped JLT (DLT) to maximize the gate control over its channel and apparently to suppress the GIDL effects as well as L-BTBT and off-state tunneling current (IOFF). Therefore, the parasitic BJT action is minimized significantly in the device by the application of field plates, which in turn, minimizes the tunneling current (IOFF) and improves the (ION/IOFF) current ratio by at least 2 orders. The on-state performance of the device is also improved and is analyzed by improved analog parameters such as Transconductance Gm (26%), intrinsic gain AV (70%), Output trans-conductance GDS (25.8%), Early voltage VEA (40.6%) and Output resistance R0 (34.63%) in comparison to conventional DLT. We have given a simplified fabrication flow for the proposed device and performed the misalignment analysis for the device. Moreover, the circuit level analysis of the device is examined on H-SPICE using lookup table model in Verilog-A.

引用

页数：9

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