Low-Power Multiple-Valued SRAM Logic Cells Using Single-Electron Devices

被引：0

作者：

Syed, Naila ^{[1
]}

Chen, Chunhong ^{[1
]}

机构：

[1] Univ Windsor, Dept Elect & Comp Engn, Windsor, ON N9B 3P4, Canada

来源：

2012 12TH IEEE CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO) | 2012年

关键词：

Single electron devices; SRAM cell; negative differential conductance; low power; multiple-valued logic; CIRCUITS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents single electron tunneling (SET) based static memory cells for multiple-valued logic applications. All simulations are conducted using Monte Carlo simulation tools. In particular, a ternary SRAM cell is designed using the proposed architecture with standby power consumption of 0.98nW and logic margin of 270mV at temperature of 77K.

引用

页数：4

共 9 条

[1] Averin D. V., 1991, Mesoscopic Phenomena in Solids, P173
[2] A 3.3-V 12-NS 16-MB CMOS SRAM
GOTO, H
OHKUBO, H
KONDOU, K
OHKAWA, M
MITANI, H
HORIBA, S
SOEDA, M
HAYASHI, F
HACHIYA, Y
SHIMIZU, T
ANDO, M
MATSUDA, Z
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (11) : 1490 - 1496
[3] Negative differential resistance due to single-electron switching
Heij, CP
Dixon, DC
Hadley, P
Mooij, JE
[J]. APPLIED PHYSICS LETTERS, 1999, 74 (07) : 1042 - 1044
[4] Ionescu A. M., 2004, P IEEE NAN, V3, P287
[5] Ionescu AM, 2002, DES AUT CON, P88, DOI 10.1109/DAC.2002.1012600
[6] A novel SET/MOSFET hybrid static memory cell design
Lee, BH
Jeong, YF
[J]. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2004, 3 (03) : 377 - 382
[7] Mahapatra S, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P323, DOI 10.1109/IEDM.2002.1175844
[8] RTD/HFET low standby power SRAM gain cell
van der Wagt, JPA
Seabaugh, AC
Beam, EA
[J]. IEEE ELECTRON DEVICE LETTERS, 1998, 19 (01) : 7 - 9
[9] SIMON - A simulator for single-electron tunnel devices and circuits
Wasshuber, C
Kosina, H
Selberherr, S
[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1997, 16 (09) : 937 - 944

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