A 12-bit 250 MS/s pipeline ADC with 78 dB SFDR in 0.13-μm CMOS

A 12-bit 250MS/s pipeline ADC is presented and implemented in 0.13 mu m CMOS process. To reduce the load capacitance of each pipeline stage and save area, the inter-metal capacitors are adopted as input sampling capacitors of the comparators. A fully integrated reference buffer associated with a simulation scheme is proposed to improve the settling speed and PSRR of the differential reference voltage. To reduce the overall power a low cost foreground calibration for capacitor mismatches is employed. The single-stage telescopic with gain-boosting amplifiers and an improved bias is applied in each stage due to its high power efficiency. Additionally, the timing in the sampling phase is optimised to achieve high sampling linearity. Even harmonics induced by parasitic capacitance are analysed profoundly and mitigated at the level of layout. The measured SNDR and SFDR are 63 and 78 dB with 38.1MHz input, respectively, and remain 63 and 77 dB with Nyquist input. The ADC core area is 1.6mm(2) and consumes 165mW (reference buffer included, LVDS excluded) at 250MS/s under 1.3V.