Low Cost, High Performance, and High Reliability 2.5D Silicon Interposer

This paper presents the first demonstration of polycrystalline silicon interposers with fine pitch through package vias (TPV), with less than 5 mu m RDL lithography at 50 mu m pitch copper microbump assembly. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. The polycrystalline Si interposer with 100-200 mu m thick raw Si, obtained without any back-grind or polish, and double side processing, without the use of carriers, has the potential to reduce the cost of wafer-based Si interposers by 2x and up to 10x by scaling to large panels. Thick polymer liner reduces the electrical loss of TPVs dramatically, by an order of magnitude compared to TSVs with SiO2 liner. Initial reliability of TPVs at 150 mu m and 200 mu m pitch was demonstrated with daisy chains passing 1000 thermal cycles from -55 degrees C to 125 degrees C. The paper concludes with Cu-SnAg microbump assembly at 50um pitch onto panel Si interposers with Cu-polymer RDL routing at 4-5 mu m line lithography.