Establishing latch correspondence for embedded circuits of PowerPC® microprocessors

被引：0

作者：

Anand, H ^{[1
]}

Bhadra, J ^{[1
]}

Sen, A ^{[1
]}

Abadir, MS ^{[1
]}

Davis, KG ^{[1
]}

机构：

[1] Freescale Semicond Inc, Austin, TX 78727 USA

来源：

HLDVT'05: TENTH ANNUAL IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present a novel latch mapping methodology that judiciously leverages structural and functional analyses on digital sequential circuits. We make use of functional design constraints in a novel way to get latch correspondence information. For scanable latches we use a technique based on scan chain analysis to obtain latch correspondences. We also provide an effective heuristic for finding latch correspondences for latches (potentially non-scanable) in complex state machines having cyclic dependencies. Our methodology not only answers latch correspondence, but also provides polarity of the correspondence. This is a major advantage over earlier latch mapping algorithms. Experimental results obtained on embedded circuits from live PowerPC (R) 1 design projects have shown that our technique fares better than a leading vendor tool in mapping latches - in both quantitative (more latches mapped) and performance (time/memory used) aspects.

引用

页码：37 / 44

页数：8