Analytical Modeling for Prediction of Chip Package-level Thermal Performance

Performance growth in high power electronics has hit a thermal barrier. High total power dissipation requirements and the presence of localized hot spots are causing chips to exceed safe junction temperature limits, and thermally aware chip package design is crucial for ensuring reliable device operation. In this paper, an analytical model is developed as an early stage design tool to predict the thermal performance of various chip package configurations. The analytical model is based on existing multi-layered conduction models in literature and accurately predicts the maximum chip junction temperature for packages with spatially non-uniform power maps to within 1% of numerical results. The reduction in computational time per case and scripting capability for large batch simulations makes the analytical model a convenient tool for parametric studies. The model is used to predict the thermal performances of bare die and lidded packages for a wide range of thermal interface material properties, power map distributions, and system cooling technologies. Results show that bare die packages are more sensitive to changes in thermal interface material properties and power map spatial non-uniformities. For certain combinations of thermal interface materials, lidded packages may have equal or improved thermal performance over bare die packages.