Enhancing timing-driven FPGA placement for pipelined netlists

被引：0

作者：

Eguro, Ken ^{[1
]}

Hauck, Scott ^{[1
]}

机构：

[1] Univ Washington, Dept Elect Engn, Seattle, WA 98195 USA

来源：

2008 45TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 | 2008年

关键词：

FPGA; placement; simulated annealing; timing-driven; pipelined;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

FPGA application developers often use pipelining, C-slowing and retiming to improve the performance of their designs. Unfortunately, registered netlists present a fundamentally different problem to CAD tools, potentially limiting the benefit of these techniques. In this paper we discuss some of the inherent issues pipelined netlists pose to existing timing-driven placement approaches. We then present two algorithmic modifications that reduce post-routing critical path delay by an average of 40%.

引用

页码：34 / 37

页数：4

共 48 条

[31] RWRoute: An Open-source Timing-driven Router for Commercial FPGAs
Zhou, Yun
Maidee, Pongstorn
Lavin, Chris
Kaviani, Alireza
Stroobandt, Dirk
ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, 2022, 15 (01)
[32] WIRELENGTH DRIVEN PLACEMENT FOR FPGA USING SOFT COMPUTING TECHNIQUE
Venuopal, Nagalakshmi
Manimegalai, R.
PROCEEDINGS OF THE IEEE INTERNATIONAL CONFERENCE ON SOFT-COMPUTING AND NETWORKS SECURITY (ICSNS 2015), 2015,
[33] Efficient optimization by modifying the objective function: Applications to timing-driven VLSI layout
Baldick, R
Kahng, AB
Kennings, A
Markov, IL
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2001, 48 (08) : 947 - 956
[34] TIMING DRIVEN PLACEMENT BASED ON FUZZY THEORY
GU, ZC
YAMADA, S
YONEDA, S
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1992, E75A (07) : 917 - 919
[35] Timing-Driven Flow-Channel Network Construction for Continuous-Flow Microfluidic Biochips
Huang, Xing
Ho, Tsung-Yi
Chakrabarty, Krishnendu
Guo, Wenzhong
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 39 (06) : 1314 - 1327
[36] TIGER: An efficient timing-driven global router for gate array and standard cell layout design
Hong, XL
Xue, TX
Huang, J
Cheng, CK
Kuh, ES
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1997, 16 (11) : 1323 - 1331
[37] Timing-Driven Titan: Enabling Large Benchmarks and Exploring the Gap between Academic and Commercial CAD
Murray, Kevin E.
Whitty, Scott
Liu, Suya
Luu, Jason
Betz, Vaughn
ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, 2015, 8 (02)
[38] Timing-Driven Non-Rectangular Obstacles-Avoiding Routing Algorithm for the X-Architecture
Huang, Hsin-Hsiung
Chang, Shu-Ping
Lin, Yu-Cheng
Hsieh, Tsai-Ming
PROCEEDINGS OF THE 8TH WSEAS INTERNATIONAL CONFERENCE ON INSTRUMENTATION, MEASUREMENT, CIRCUITS AND SYSTEMS: INSTRUMENTATION, MEASUREMENT, ELECTRONICS, CIRCUITS AND SYSTEMS, 2009, : 31 - +
[39] A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design
Xu, J
Hong, XL
Jing, T
Cai, YC
Gu, J
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2003, E86A (12) : 3158 - 3167
[40] A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design
Xu, Jingyu
Hong, Xianlong
Jing, Tong
Zhang, Ling
Gu, Jun
INTEGRATION-THE VLSI JOURNAL, 2006, 39 (04) : 457 - 473

← 1 2 3 4 5 →