An Energy and Area Efficient SC SAR ADC Structure Based on Multi Level Capacitor Switching Technique

被引：0

作者：

Ghoshal, Pranati ^{[1
]}

Moydudy, M. ^{[2
]}

Hossain, M. ^{[3
]}

Sen, Sunit Kr. ^{[4
]}

机构：

[1] Techno India, AEIE Dept, Kolkata, India

[2] N Cal Polytech Coll, AEIE Dept, Kolkata, India

[3] TCS, IT In Charge, Kolkata, India

[4] Univ Calcutta, Dept Appl Phys, Kolkata, India

来源：

PROCEEDINGS OF 2ND INTERNATIONAL CONFERENCE ON 2017 DEVICES FOR INTEGRATED CIRCUIT (DEVIC) | 2017年

关键词：

Capacitor array; energy saving; tri-level switching; asymmetric monotonic switching; binary search algorithm; unit capacitor; SCHEME;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new capacitor array structure which is both energy and area efficient is presented for a 4 bit successive approximation register (SAR) analog-to-digital converter (ADC). The proposed circuit consumes zero energy in the second and third comparison cycles. Significant lowering of energy in the different charge redistribution steps is ensured by applying different voltages in the switching scheme of the various comparison cycles. Besides energy saving to the extent of 98%, a 75% reduction in capacitance is achieved compared to the conventional method.

引用

页码：574 / 577

页数：4

共 13 条

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