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- [2] MULTISCALE MODELS FOR ELECTROPLATING OF THROUGH SILICON VIAS 2018 INTERNATIONAL WAFER LEVEL PACKAGING CONFERENCE (IWLPC), 2018,
- [3] Numerical Simulation and Experimental Verification of Copper Plating with Different Additives for Through Silicon Vias 2012 4TH ELECTRONIC SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE (ESTC), 2012,
- [6] Experimental Stress Characterization and Numerical Simulation for Copper Pumping Analysis of Through-Silicon Vias IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2016, 6 (07): : 995 - 1001
- [7] Fabrication and characteristics of through silicon vias interconnection by electroplating Jpn. J. Appl. Phys., 1 PART 3
- [10] Thermo-mechanical Reliability of Copper-filled and Polymer-filled Through Silicon Vias in 3D Interconnects 2013 IEEE 63RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2013, : 2132 - 2137