Design of Novel Testable and Diagnosable Phase-Frequency Detector

被引：2
作者：
Gholami, Mohammad [1 ]
Baleghi, Yasser [1 ]
Ardeshir, Gholamreza [1 ]
机构：
[1] Babol Noshirvani Univ Technol, Dept Elect Engn, Babol Sar, Iran
来源：
CIRCUITS SYSTEMS AND SIGNAL PROCESSING | 2014年 / 33卷 / 04期
关键词：
Phase-Frequency Detector; PFD; DLL; PLL; Testable; Diagnosable; DLL; ARCHITECTURE; JITTER;
D O I：
10.1007/s00034-013-9679-z
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a novel fully testable and diagnosable structure for phase-frequency detectors. All procedures of converting the conventional PFD to the fully testable one are reported step by step. Also, the probability-based testability of proposed architecture is calculated. In addition, area considerations related to new fully testable PFD are introduced completely. At last, the proposed structure is designed in both system level and circuit level. The results of fully testable PFD in 0.13-mu m CMOS technology are shown. Simulation results confirm the theoretical analysis.
引用
收藏
页码：999 / 1018
页数：20
相关论文
共 24 条
[1]  
Abdel-Hafez K.S., 2004, U.S. Patent Application, Patent No. [No. 20040153926, 20040153926]
[2]  
Abramovici M., 1994, Digital Systems Testing and Testable Design
[3]  
[Anonymous], IEEE S IND EL APPL I
[4]   VLSI TEST STRATEGY PLANNING TECHNIQUES AND TOOLS. [J].
Baker, K. ;
Croft, R.M. .
Computer-aided engineering journal, 1987, 4 (02) :83-88
[5]  
Bickford JP, 2012, ASMC PROC, P16, DOI 10.1109/ASMC.2012.6212861
[6]   The use of model-based test requirements throughout the product life cycle [J].
Bukata, E ;
Davis, DC ;
Shombert, L .
IEEE AEROSPACE AND ELECTRONIC SYSTEMS MAGAZINE, 2000, 15 (02) :39-44
[7]   A 0.5-5-GHz wide-range multiphase DLL with a calibrated charge pump [J].
Chuang, Chi-Nan ;
Liu, Shen-Iuan .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2007, 54 (11) :939-943
[8]   Getting errors to catch themselves - Self-testing of VLSI circuits with built-in hardware [J].
Das, SR .
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2005, 54 (03) :941-955
[9]   A novel architecture for low voltage-low power DLL-based frequency multipliers [J].
Gholami, M. ;
Ardeshir, Gh. ;
Ghonoodi, H. .
IEICE ELECTRONICS EXPRESS, 2011, 8 (11) :859-865
[10]   Analysis of DLL Jitter due to Voltage-Controlled Delay Line [J].
Gholami, Mohammad ;
Ardeshir, Gholamreza .
CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2013, 32 (05) :2119-2135
123