A Fully RNS based ECC Processor

被引：16

作者：

Asif, Shahzad ^{[1
]}

Hossain, Md Selim ^{[1
]}

Kong, Yinan ^{[1
]}

Abdul, Wadood ^{[2
]}

机构：

[1] Macquarie Univ, Dept Engn, Sydney, NSW 2109, Australia

[2] King Saud Univ, Coll Comp & Informat Sci, Dept Comp Engn, Riyadh, Saudi Arabia

来源：

INTEGRATION-THE VLSI JOURNAL | 2018年 / 61卷

关键词：

Residue number system (RNS); Modular multiplier; Montgomery multiplier; Elliptic curve cryptography (ECC); Elliptic curve point multiplication (ECPM); ECC processor (ECP); Field programmable gate array (FPGA); CURVE CRYPTOGRAPHIC PROCESSOR; SCALAR MULTIPLICATIONS; HARDWARE; RESISTANT; GF(P);

D O I：

10.1016/j.vlsi.2017.11.010

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This work proposes a residue number system (RNS) based hardware architecture of an elliptic curve cryptography (ECC) processor over prime field. The processor computes point multiplication in Jacobian coordinates by a combined architecture of point doubling and point addition. An optimized modular reduction architecture is also presented that achieves low area by dividing the RNS moduli in small groups and processes the groups one by one. The proposed ECC processor is generic and supports any random curve over F(p)256. The implementation on Virtex-7 and Virtex-6 FPGAs shows comparable performance to the state-of-the-art binary and RNS based ECC processors.

引用

页码：138 / 149

页数：12

共 39 条

[1] Fast and Flexible Hardware Support for ECC Over Multiple Standard Prime Fields [J].