A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning

被引:0
|
作者
Kimura, Shuta [1 ]
Hashimoto, Masanori [1 ]
Onoye, Takao [1 ]
机构
[1] Osaka Univ, Dept Informat Syst Engn, Suita, Osaka 5650871, Japan
关键词
post-silicon tuning; body bias clustering; process variation; body biasing; statistical static timing analysis; OPTIMIZATION; POWER;
D O I
10.1587/transfun.E95.A.2292
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Post-silicon tuning is attracting a lot of attention for coping with increasing process variation. However, its tuning cost via testing is still a crucial problem. In this paper, we propose tuning-friendly body bias clustering with multiple bias voltages. The proposed method provides a small set of compensation levels so that the speed and leakage current vary monotonically according to the level. Thanks to this monotonic leveling and limitation of the number of levels, the test-cost of post-silicon tuning is significantly reduced. During the body bias clustering, the proposed method explicitly estimates and minimizes the average leakage after the post-silicon tuning. Experimental results demonstrate that the proposed method reduces the average leakage by 25.3 to 51.9% compared to non clustering case. In a test case of four clusters, the number of necessary tests is reduced by 83% compared to the conventional exhaustive test approach. We reveal that two bias voltages are sufficient when only a small number of compensation levels are allowed for test-cost reduction. We also give an implication on how to synthesize a circuit to which post-silicon tuning will be applied.
引用
收藏
页码:2292 / 2300
页数:9
相关论文
共 50 条
  • [11] Study of Low-Cost Electrical Test Strategies for Post-Silicon Yield Improvement of MEMS Convective Accelerometers
    Ahmed Amine Rekik
    Florence Azaïs
    Frédérick Mailly
    Pascal Nouet
    Journal of Electronic Testing, 2014, 30 : 87 - 100
  • [12] A New Algorithm for Post-Silicon Clock Measurement and Tuning
    Lak, Zahra
    Nicolici, Nicola
    2011 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT), 2011, : 53 - 59
  • [13] Study of Low-Cost Electrical Test Strategies for Post-Silicon Yield Improvement of MEMS Convective Accelerometers
    Rekik, Ahmed Amine
    Azais, Florence
    Mailly, Frederick
    Nouet, Pascal
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2014, 30 (01): : 87 - 100
  • [14] Post-silicon Test Flow for Aging Prediction
    Gao, Zih-Huan
    Hsu, Hau
    Hsu, Ting-Shuo
    Liou, Jing-Jia
    2017 IEEE 26TH ASIAN TEST SYMPOSIUM (ATS), 2017, : 66 - 71
  • [15] On the Quality of Test Vectors for Post-Silicon Characterization
    Sauer, Matthias
    Czutro, Alexander
    Becker, Bernd
    Polian, Ilia
    2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), 2012,
  • [16] Design-time optimization of post-silicon tuned circuits using adaptive body bias
    Kulkarni, Sarvesh H.
    Sylvester, Dennis M.
    Blaauw, David T.
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2008, 27 (03) : 481 - 494
  • [17] Timing-Test Scheduling for Constraint-Graph Based Post-Silicon Skew Tuning
    Kaneko, Mineo
    2012 IEEE 30TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 2012, : 460 - 465
  • [18] TuneLogic: Post-Silicon Tuning of Dual-Vdd Designs
    Bijansky, Stephen
    Lee, Sae Kyu
    Aziz, Adnan
    ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2, 2009, : 394 - 400
  • [19] Analog/RF Post-silicon Tuning via Bayesian Optimization
    Pan, Renjian
    Tao, Jun
    Su, Yangfeng
    Zhou, Dian
    Zeng, Xuan
    Li, Xin
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2020, 25 (01)
  • [20] Tier Adaptive Body Biasing: A Post-Silicon Tuning Method to Minimize Clock Skew Variations in 3-D ICs
    Chae, Kwanyeob
    Zhao, Xin
    Lim, Sung Kyu
    Mukhopadhyay, Saibal
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2013, 3 (10): : 1720 - 1730