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- [1] Body Bias Clustering for Low Test-Cost Post-Silicon Tuning 2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2012, : 283 - 289
- [2] A statistical framework for post-silicon tuning through body bias clustering IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, ICCAD, 2006, : 207 - +
- [4] Margin Aware Timing Test and Tuning Algorithm for Post-Silicon Skew Tuning 2017 IEEE 60TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2017, : 1244 - 1247
- [5] Clustering for Reduction of Power Consumption and Area on Post-Silicon Delay Tuning 2018 7TH IEEE INTERNATIONAL SYMPOSIUM ON NEXT-GENERATION ELECTRONICS (ISNE), 2018, : 86 - 89
- [6] A Robust Architecture for Post-Silicon Skew Tuning 2011 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2011, : 774 - 778
- [7] Yield and Power Improvement Method by Post-Silicon Delay Tuning and Technology Mapping 2016 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS), 2016, : 366 - 369
- [8] Active Learning Framework for Post-Silicon Variation Extraction and Test Cost Reduction 2010 IEEE AND ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2010, : 508 - 515
- [10] AutoRex: An Automated Post-Silicon Clock Tuning Tool ITC: 2009 INTERNATIONAL TEST CONFERENCE, 2009, : 110 - +