BTI reliability of 45 nm high-k plus metal-gate process technology

被引：95

作者：

Pae, S. ^{[1
]}

Agostinelli, M. ^{[1
]}

Brazie, M. ^{[2
]}

Chau, R.

Dewey, G.

Ghani, T. ^{[2
]}

Hattendorf, M. ^{[2
]}

Hicks, J. ^{[1
]}

Kavalieros, J.

Kuhn, K.

Kuhn, M. ^{[1
,2
]}

Maiz, J. ^{[1
]}

Metz, M.

Mistry, K. ^{[2
]}

Prasad, C. ^{[1
]}

Ramey, S. ^{[1
]}

Roskowski, A. ^{[2
]}

Sandford, J. ^{[2
]}

Thomas, C. ^{[2
]}

Thomas, J. ^{[1
]}

Wiegand, C. ^{[2
]}

Wiedemer, J. ^{[2
]}

机构：

[1] Intel Corp, 5200 NE Elam Young Pkwy, Hillsboro, OR 97124 USA

[2] PTD, Hillsboro, OR 97124 USA

来源：

2008 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 46TH ANNUAL | 2008年

关键词：

BTI; high-K; metal gate; transistors; reliability;

D O I：

10.1109/RELPHY.2008.4558911

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, Bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and final HK process demonstrated NMOS and PMOS BTI on HK+MG transistors that are better than that of SiON at matched E-fields and comparable at targeted 30% higher use fields. The final process also showed no hysteresis due to fast traps thereby allowing us to characterize its intrinsic degradation mechanism. On the optimized process, NMOS BTI is attributed primarily to electron trapping in the HK bulk and HK/SiON interfacial layer (IL) regions. PMOS BTI degradation, on the other hand, is mainly interface driven and is found to be very similar to that observed on conventional SiON transistors.

引用

页码：352 / +

页数：3

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