Design of packet classification co-processor with FPGA

Even with HiCuts algorithm, which is one of the most effective algorithms for packet classification, the on-line searching for each input packet still consumes the main CPU a large amount of computation resource if it is fulfilled by software. An effective alternative is to use a hardware co-processor to realize the on-line searching. Based on the principle of HiCuts algorithm, the architecture design of a hardware on-line searching co-processor with an FPGA is presented in this paper Utilizing multiple pipeline structure, there are a total of 12 searching engines working parallel. The co-processor only consumes a small part of logic resource of FPGA but can achieve very high searching speed (8M packet heads/second). Furthermore the simulation test results show that the searching speed of the co-processor is not sensitive to the number of rules in the classifier; the memory consumption curve can be a very useful guide for the optimization of off-line classifier pre-processing.