Multichannel mixed-mode IC for digital readout of silicon strip detectors

The design of a mixed mode 64-channel ASIC for digital readout of silicon strip detectors used in X-ray imaging applications is presented, The design is implemented in a 0.8 mum CMOS ell epi-type substrate technology. The single channel consists of a charge sensitive preamplifier. a shaping amplifier. a discriminator and a pseudo-random 20-bit counter. In addition to the 64-channel core which is responsible for signal processing and data storage, the IC comprises additional blocks like an internal calibration circuit, internal DACs and a command decoder which governs communication of the IC with the external world. Those blocks have been designed keeping in mind testability features and using the chips for building multi-chip modules. The equivalent input noise charge measured at room temperature for a detector capacitance of 2.5 pF and signal integration time of 0.7 mus is 167 e(-) rms. The average power dissipation is 2.5 mW/channel. The channel-to-channel offset spread referred to the input is only 28 e(-) rms, while the standard deviation of gain spread is 0.5% of the mean value. The chip occupies area of 2.8 x 6.5 mm(2). (C) 2002 Elsevier Science Ltd. All rights reserved.