Current tunnelling through MOS devices

被引：9

作者：

Bouazra, A. ^{[1
]}

Nasrallah, S. Abdi-Ben ^{[1
]}

Poncet, A. ^{[2
]}

Said, M. ^{[1
]}

机构：

[1] Fac Sci Monastir, Dept Phys, Unite Rech Phys Solides, Monastir 5019, Tunisia

[2] Inst Natl Sci Appl, Phys Mat Lab, UMR CNRS 5511, F-69621 Villeurbanne, France

来源：

MATERIALS SCIENCE & ENGINEERING C-BIOMIMETIC AND SUPRAMOLECULAR SYSTEMS | 2008年 / 28卷 / 5-6期

关键词：

tunnelling; high-k dielectric; I-V; trap;

D O I：

10.1016/j.msec.2007.10.010

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

In this study, we have calculated the tunnelling current through ultra thin gate oxides for MOS structure. In the aim to reduce the large gate leakage while scaling SiO2 down oxide thickness, it has become necessary to use high-k gate dielectrics. We have used HfO2/SiO2 dual layer as gate oxide. According to the importance of these alternative gate dielectrics, it becomes essential to take into account the existence of electron trap at the HfO2/SiO2 interface. The gate current of n poly-Si/HfO2/trap/SiO2/p Si substrate capacitors is underestimated for low voltage if the effect of traps is not taken into account. The influence of trap parameters like width, depth and material masse on gate current has been examined. (c) 2007 Elsevier B.V. All rights reserved.

引用

页码：662 / 665

页数：4

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