The effects of RET on process capability for 45nm technology node

被引:0
|
作者
Zhang, F [1 ]
Li, YQ [1 ]
机构
[1] Chinese Acad Sci, Inst Elect Engn, 6 Bei Er Tiao, Beijing 100080, Peoples R China
来源
2ND INTERNATIONAL CONFERENCE ON ADVANCED OPTICAL MANUFACTURING AND TESTING TECHNOLOGIES: ADVANCED OPTICAL MANUFACTURING TECHNOLOGIES | 2006年 / 6149卷
关键词
RET; process capability; polarization; immersion lithography; PROLITH;
D O I
10.1117/12.674216
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
One of the main factors driving ICs in complexity is the improvement in photolithography to print small features. The use of immersion imaging and resolution enhancement technology (RET) will extend the ArF lithography to produce small features. With the patterns size decreasing, the absolute CD variation has a bigger relative importance on small features. The process windows are used to see if a certain process is compatible with the dose and focus budget. We discuss the impact of illumination, numeric aperture, phase-shifting mask and polarized light on process windows using ArF immersion lithography to print line pattern exposed features in photo resist on 45nm node. The interaction between the process windows and illumination, numeric aperture, phase-shifting mask and polarized light are calculated using a full photo resist model. The analysis gives fundamental insight into the optimum conditions necessary for printing these patterns both individually and simultaneously. The results show that illumination, numeric aperture, phase-shifting mask and polarized light can contribute to the process capability. The dipole illumination system can enhance the process window about twice than that use conventional illumination. The process capability of semi-dense pattern is insensitive to optical parameters. The 100% attPSMs and altPSMs are strong phase shifting mask, so the process capability can be enhanced. By using the polarized light can enlarge the depth of focus about 4%similar to 11% with specified exposure latitude. According to the rules of process windows, some methods to extend process windows are presented.
引用
收藏
页数:6
相关论文
共 50 条
  • [21] Challenges in implementing high-K dielectrics in the 45nm technology node
    Lee, BH
    Song, SC
    Choi, R
    Wen, HC
    Majhi, P
    Kirsch, P
    Young, C
    Bersuker, G
    2005 INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, 2005, : 73 - 76
  • [22] Solutions for logic and processor core design at the 45nm technology node & and below
    Royannez, Philippe
    Mair, Hugh
    Clinton, Michael
    Ko, Uming
    2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4, 2007, : 923 - 926
  • [23] Wafer flatness requirements for 45nm node (65nm hp) lithography process
    Okazaki, Motoya
    Ciari, R.
    James, L.
    Meng, B.
    Thompson, M.
    Dai, H.
    Xu, X.
    Liu, I.
    Dorflinger, D.
    Yung, B.
    Ngai, C.
    2008 IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE, 2008, : 356 - 358
  • [24] Patterning capability and limitations by pattern collapse in 45nm and below node photo mask production
    Hwang, Guen-Ho
    Patil, Manish
    Seo, Soon-Kyu
    Yu, Chu-Bong
    Hur, Ik-Boum
    Kim, Dong Hyun
    Shin, Cheol
    Jung, Sung-Mo
    Lee, Yong-Hyun
    Choi, Sang-Soo
    PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY XV, PTS 1 AND 2, 2008, 7028
  • [25] Air gap integration for the 45nm node and beyond
    Daamen, R
    Verheijden, GJAM
    Bancken, PHL
    Vandeweyer, T
    Michelon, J
    Hoang, VN
    Hoofman, RJOM
    Gallagher, MK
    PROCEEDINGS OF THE IEEE 2005 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2005, : 240 - 242
  • [26] Mask Inspection method for 45nm node device
    Oh, Sunghyun
    Choi, Yongkyoo
    Hwang, Daeho
    Jeong, Goornin
    Han, Oscar
    PHOTOMASK TECHNOLOGY 2007, PTS 1-3, 2007, 6730
  • [27] Metal gate technology for 45nm and beyond
    Shibahara, Kentaro
    2006 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS, 2006, : 105 - 106
  • [28] Hyper NA model validation for the 45nm node
    Palmer, Shane R.
    Bai, Min
    van Adrichem, Paul J. M.
    DATA ANALYSIS AND MODELING FOR PROCESS CONTROL III, 2006, 6155
  • [29] Water immersion optical lithography for the 45nm node
    Smith, BW
    Kang, H
    Bourov, A
    Cropanese, F
    Fan, YF
    OPTICAL MICROLITHOGRAPHY XVI, PTS 1-3, 2003, 5040 : 679 - 689
  • [30] Options at the 45nm node include engineered substrates
    Moroz, V
    Pramanik, D
    Henley, F
    Ong, P
    SOLID STATE TECHNOLOGY, 2005, 48 (07) : 77 - +