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- [21] Challenges in implementing high-K dielectrics in the 45nm technology node 2005 INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, 2005, : 73 - 76
- [22] Solutions for logic and processor core design at the 45nm technology node & and below 2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4, 2007, : 923 - 926
- [23] Wafer flatness requirements for 45nm node (65nm hp) lithography process 2008 IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE, 2008, : 356 - 358
- [24] Patterning capability and limitations by pattern collapse in 45nm and below node photo mask production PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY XV, PTS 1 AND 2, 2008, 7028
- [25] Air gap integration for the 45nm node and beyond PROCEEDINGS OF THE IEEE 2005 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2005, : 240 - 242
- [27] Metal gate technology for 45nm and beyond 2006 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS, 2006, : 105 - 106
- [28] Hyper NA model validation for the 45nm node DATA ANALYSIS AND MODELING FOR PROCESS CONTROL III, 2006, 6155
- [29] Water immersion optical lithography for the 45nm node OPTICAL MICROLITHOGRAPHY XVI, PTS 1-3, 2003, 5040 : 679 - 689