RHBD techniques for mitigating effects of single-event hits using guard-gates

被引：106
作者：
Balasubramanian, A
Bhuva, BL
Black, JD
Massengill, LW
机构：
[1] Vanderbilt Univ, Dept Elect Engn, Nashville, TN 37232 USA
[2] Vanderbilt Univ, Inst Space Def & Elect, Nashville, TN 37235 USA
来源：
IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2005年 / 52卷 / 06期
关键词：
complementary metal-oxide-semiconductor (CMOS); single-event hits; single-event transient (SET); transient pulsewidth;
D O I：
10.1109/TNS.2005.860719
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Hardening-by-design techniques to mitigate the effect of single-event transients (SET) using guard-gates are developed. Design approaches for addressing combinational logic hits and storage cell hits are presented. Simulation results show that the designs using guard-gates are less susceptible to single-event hits. Area, power, and speed penalty for guard-gate designs for combinational logic are found to be minimal. For latches, the area penalty is higher but speed penalty is minimal.
引用
收藏
页码：2531 / 2535
页数：5
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