Low Power and Memory Efficient FFT Architecture Using Modified CORDIC Algorithm

被引：0
|
作者：
Malashri, A. [1 ]
Paramasivam, C. [1 ]
机构：
[1] KS Rangasamy Coll Technol, Dept ECE, Tiruchengode, Tamil Nadu, India
来源：
2013 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES) | 2013年
关键词：
FFT; CORDIC; VLSI; Low power; PROCESSOR;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a pipelined, reduced memory and low power CORDIC-based architecture for fast Fourier transform implementation. The proposed algorithm utilizes a new addressing scheme and the associated angle generator logic in order to remove any ROM usage for storing twiddle factors. CORDIC is implemented by a simple hardware through repeated shift-add operations Low power is achieved by the using the Coordinate Rotation Digital Computer algorithm in the place of conventional multiplication and furthermore, dynamic power consumption is reduced with no delay penalties.
引用
收藏
页码：1041 / 1046
页数：6
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