Memory Efficient Hardware Accelerator for Kernel Support Vector Machine Based Pedestrian Detection

Pedestrian detection being a vital as well as complex problem poses a unique challenge from accuracy and complexity point of view. On-chip memory requirement is one of the key issues for sliding window based detectors. In this paper a memory efficient hardware architecture is proposed which estimates the weights from a partially stored model at runtime. It uses a simple and robust feature with histogram intersection classifier. The implementation results show 80% reduction in logic resources and 46% reduction in memory without sacrificing accuracy as compared to the state of the art hardware implementations.