A 2.5Gbit/s pipelined routing engine for input-queued ATM switches

被引：0

作者：

Jeong, GJ ^{[1
]}

Lee, JH ^{[1
]}

Lee, BC ^{[1
]}

机构：

[1] Kyongju Univ, Sch Elect & Comp Engn, Kyongju 780712, South Korea

来源：

IEEE REGION 10 INTERNATIONAL CONFERENCE ON ELECTRICAL AND ELECTRONIC TECHNOLOGY, VOLS 1 AND 2 | 2001年

关键词：

ATM; input-queued switch; pipelined routing engine; transmission latency; virtual output queue;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents the design of a 2.5Gbit/s pipelined virtual output queue routing engine for an input-queued ATM switch, which has a serial cross bar structure. The proposed routing engine has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the routing engine and central arbiter using a new request control method that is based on a high-speed shifter. The designed routing engine has been implemented in a field programmable gate array chip with a 77MHz operating frequency, a 900-pin fine ball grid array package, and 16x16 switch size.

引用

页码：377 / 380

页数：4

共 6 条

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