MONOLITHIC SENSORS IN DEEP SUBMICRON CMOS TECHNOLOGY FOR LOW MATERIAL BUDGET, HIGH RATE HEP APPLICATIONS

被引:0
|
作者
Andreoli, C. [1 ,2 ]
Ratti, L. [1 ,2 ]
Manghisoni, M. [2 ,3 ]
Traversi, G. [2 ,3 ]
机构
[1] Univ Pavia, Dipartimento Elettron, Via Ferrata 1, I-27100 Pavia, Italy
[2] Ist Nazl Fis Nucl, Sez Pavia, I-27100 Pavia, Italy
[3] Univ Bergamo, Dipartimento Ingn Ind, I-24044 Dalmine, Italy
关键词
MAPS; CMOS deep submicron; sparsified digital readout;
D O I
10.1142/9789812819093_0003
中图分类号
O59 [应用物理学];
学科分类号
摘要
This work aims at discussing the development of monolithic active pixel sensors (MAPS), which are considered as possible candidate detectors for the inner layers at the future large colliders. In such devices the triple well option, available in deep submicron CMOS technologies, is exploited to implement analog and digital signal processing at the pixel level. In this scheme, the charge collecting electrode is laid out using a deep n-well (DNW) and a full readout chain for capacitive detectors is integrated in the elementary cell. In particular, this work is concerned with the design and performance of DNW monolithic sensor prototypes fabricated in a 130 nm CMOS technology, including different test structures and performing pixel-level charge amplification, shaping and data sparsification.
引用
收藏
页码:18 / +
页数:2
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