Through-glass copper via using the glass reflow and seedless electroplating processes for wafer-level RF MEMS packaging

被引:66
作者
Lee, Ju-Yong [1 ]
Lee, Sung-Woo [1 ]
Lee, Seung-Ki [1 ]
Park, Jae-Hyoung [1 ]
机构
[1] Dankook Univ, Dept Elect & Elect Engn, Yongin 448701, South Korea
基金
新加坡国家研究基金会;
关键词
HIGH-ASPECT-RATIO; HIGH-DENSITY; SILICON; INTERCONNECTION; TECHNOLOGY; VIAS;
D O I
10.1088/0960-1317/23/8/085012
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We present a novel method for the fabrication of void-free copper-filled through-glass-vias (TGVs), and their application to the wafer-level radio frequency microelectromechanical systems (RF MEMS) packaging scheme. By using the glass reflow process with a patterned silicon mold, a vertical TGV with smooth sidewall and fine pitch could be achieved. Bottom-up void-free filling of the TGV is successfully demonstrated through the seedless copper electroplating process. In addition, the proposed process allows wafer-level packaging with glass cap encapsulation using the anodic bonding process, since the reflowed glass interposer is only formed in the device area surrounded with silicon substrate. A simple coplanar waveguide (CPW) line was employed as the packaged device to evaluate the electrical characteristics and thermo-mechanical reliability of the proposed packaging structure. The fabricated packaging structure showed a low insertion loss of 0.116 dB and a high return loss of 35.537 dB at 20 GHz, which were measured through the whole electrical path, including the CPW line, TGVs and contact pads. An insertion loss lower than 0.1 dB and a return loss higher than 30 dB could be achieved at frequencies of up to 15 GHz, and the resistance of the single copper via was measured to be 36 m Omega. Furthermore, the thermo-mechanical reliability of the proposed packaging structure was also verified through thermal shock and pressure cooker test.
引用
收藏
页数:10
相关论文
共 33 条
[1]   Through silicon via copper electrodeposition for 3D integration [J].
Beica, Rozalia ;
Sharbono, Charles ;
Ritzdorf, Tom .
58TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, PROCEEDINGS, 2008, :577-+
[2]   Wafer-Level Package With Simultaneous TSV Connection and Cavity Hermetic Sealing by Solder Bonding for MEMS Device [J].
Cao, Yuhan ;
Ning, Wenguo ;
Luo, Le .
IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, 2009, 32 (03) :125-132
[3]   Reliability study of hermetic wafer level MEMS packaging with through-wafer interconnect [J].
Choa, Sung-Hoon .
MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2009, 15 (05) :677-686
[4]  
Department of Defense Test Method Standard Microcircuits, MILSTD883F DEP DEF T
[5]   Fabrication and electrical characterization of high aspect ratio poly-silicon filled through-silicon vias [J].
Dixit, Pradeep ;
Vehmas, Tapani ;
Vahanen, Sami ;
Monnoyer, Philippe ;
Henttinen, Kimmo .
JOURNAL OF MICROMECHANICS AND MICROENGINEERING, 2012, 22 (05)
[6]   Wire-bonded through-silicon vias with low capacitive substrate coupling [J].
Fischer, A. C. ;
Grange, M. ;
Roxhed, N. ;
Weerasekera, R. ;
Pamunuwa, D. ;
Stemme, G. ;
Niklaus, F. .
JOURNAL OF MICROMECHANICS AND MICROENGINEERING, 2011, 21 (08)
[7]  
Fischer AC, 2011, PROC IEEE MICR ELECT, P37, DOI 10.1109/MEMSYS.2011.5734356
[8]   High speed anisotropic etching of Pyrex® for microsystems applications [J].
Goyal, Abhijat ;
Hood, Vincent ;
Tadigadapa, Srinivas .
JOURNAL OF NON-CRYSTALLINE SOLIDS, 2006, 352 (6-7) :657-663
[9]  
Haque R. M., 2011, TRANSDUCERS 2011 - 2011 16th International Solid-State Sensors, Actuators and Microsystems Conference, P2303, DOI 10.1109/TRANSDUCERS.2011.5969539
[10]  
Haque RM, 2011, PROC IEEE MICR ELECT, P995, DOI 10.1109/MEMSYS.2011.5734595