Circuit techniques for a 1.8-V-only NAND flash memory

Focusing on internal high-voltage (V-pp) switching and generation for low-voltage NAND flash memories, this paper describes a V-pp switch, row decoder, and charge-pump circuit. The proposed nMOS V-pp switch is composed of only intrinsic high-voltage transistors without channel implantation, which realizes both reduction of the minimum operating voltage and elimination of the V-pp leakage current. The proposed row decoder scheme is described in which all blocks are in selected state in standby so as to prevent standby current from flowing through the proposed V-pp switches in the row decoder. A merged charge-pump scheme generates a plurality of voltage levels with an individually optimized efficiency, which reduces circuit area in comparison with the conventional scheme that requires a separate charge-pump circuit for each voltage level. The proposed circuits were implemented on an experimental NAND flash memory. The charge pump and V-pp switch successfully operated at a supply voltage of 1.8 V with a standby current of 10 muA. The proposed pump scheme reduced the area required for charge-pump circuits by 40%.