Design and Performance Analysis for the Reversible Realization of Adder/Subtractor Circuit

被引：0
|
作者：
Shukla, Vandana [1 ]
Singh, O. P. [1 ]
Mishra, G. R. [1 ]
Tiwari, R. K. [2 ]
机构：
[1] Amity Univ, Lucknow Campus, Lucknow, Uttar Pradesh, India
[2] Dr RML Avadh Univ, Dept Phys & Elect, Faizabad, Uttar Pradesh, India
来源：
2017 INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN COMPUTING AND COMMUNICATION TECHNOLOGIES (ICETCCT) | 2017年
关键词：
Reversible logic; Reversible circuit designing; N-Bit Adder/Subtractor; Quantum cost; LOGIC;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
Digital circuits have been basically applied to every field of life. Low power efficient systems are the need of this era. Reversible logic approach is the basic outcome of this necessity. Reversible technology is widely applicable in the field of nanotechnology, low power CMOS design, optical computing etc. Reversible approach basically aims to redesign any digital circuit with reversible design units. Here, we propose an efficient approach to design N-bit Adder/subtractor using reversible approach. Based on proposed N-bit Adder/Subtractor design we have also compared 4-bit, 8-bit and 16-bit circuits with the existing designs. Proposed designs are simulated and synthesized with Xilinx Spartan 3E for Device XC3S500E at 200 MHz frequency.
引用
收藏
页码：162 / 167
页数：6
相关论文
共 50 条
  • [1] Design of Optimized Reversible Binary Adder/Subtractor and BCD Adder
    Nagamani, A. N.
    Ashwin, S.
    Agrawal, Vinod Kumar
    2014 INTERNATIONAL CONFERENCE ON CONTEMPORARY COMPUTING AND INFORMATICS (IC3I), 2014, : 774 - 779
  • [2] Analysis and Design of Reversible Excess-3 Adder and Subtractor
    Nayak, V. Shiva Prasad
    Ramchander, N.
    Reddy, R. Sumanth
    Marandi, Tapas
    2016 IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT), 2016, : 397 - 400
  • [3] Performance Parameters Optimization and Implementation of Adder/Subtractor Circuit Using Reversible Logic Approach
    Shukla, Vandana
    Singh, O. P.
    Mishra, G. R.
    Tiwari, R. K.
    2016 11TH INTERNATIONAL CONFERENCE ON INDUSTRIAL AND INFORMATION SYSTEMS (ICIIS), 2016, : 323 - 328
  • [4] Design of a Novel Reversible Full Adder and Reversible Full Subtractor
    AnanthaLakshmi, A. V.
    Sudha, G. F.
    ADVANCES IN COMPUTING AND INFORMATION TECHNOLOGY, VOL 3, 2013, 178 : 623 - 632
  • [5] Design of Efficient Reversible Parallel Binary Adder/Subtractor
    Rangaraju, H. G.
    Venugopal, U.
    Muralidhara, K. N.
    Raja, K. B.
    COMPUTER NETWORKS AND INFORMATION TECHNOLOGIES, 2011, 142 : 83 - +
  • [6] A Novel Approach for Reversible Realization of 8-Bit Adder-Subtractor Circuit with Optimized Quantum Cost
    Shukla, Vandana
    Singh, O. P.
    Mishra, G. R.
    Tiwari, R. K.
    FIRST INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ENGINEERING, TECHNOLOGY AND SCIENCE - ICETETS 2016, 2016,
  • [7] Quantum Gate Implementation of a Novel Reversible Half Adder and Subtractor Circuit
    Jain, Ritika
    Sarma, Rajkumar
    2ND INTERNATIONAL CONFERENCE ON INTELLIGENT CIRCUITS AND SYSTEMS (ICICS 2018), 2018, : 72 - 76
  • [8] Reversible Adder/Subtractor with Overflow Detector
    Sultana, Sayeeda
    Radecka, Katarzyna
    2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2011,
  • [9] Design of high-performance QCA incrementer/decrementer circuit based on adder/subtractor methodology
    Safoev, Nuriddin
    Jeon, Jun-Cheol
    MICROPROCESSORS AND MICROSYSTEMS, 2020, 72
  • [10] New Design of Reversible Full Adder/Subtractor Using R Gate
    Montaser, Rasha
    Younes, Ahmed
    Abdel-Aty, Mahmoud
    INTERNATIONAL JOURNAL OF THEORETICAL PHYSICS, 2019, 58 (01) : 167 - 183
12345