MOCA: an Inter/Intra-Chip Optical Network for Memory

被引：2

作者：

Wang, Zhehui ^{[1
]}

Pang, Zhengbin ^{[2
]}

Yang, Peng ^{[1
]}

Xu, Jiang ^{[1
]}

Chen, Xuanqi ^{[1
]}

Maeda, Rafael K. V. ^{[1
]}

Wang, Zhifei ^{[1
]}

Duong, Luan H. K. ^{[1
]}

Li, Haoran ^{[1
]}

Wang, Zhe ^{[1
]}

机构：

[1] Hong Kong Univ Sci & Technol, Hong Kong, Hong Kong, Peoples R China

[2] Natl Univ Def Technol, Changsha, Hunan, Peoples R China

来源：

PROCEEDINGS OF THE 2017 54TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC) | 2017年

关键词：

D O I：

10.1145/3061639.3062286

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The memory wall problem is due to the imbalanced developments and separation of processors and memories. It is becoming acute as more and more processor cores are integrated into a single chip and demand higher memory bandwidth through limited chip pins. Optical memory interconnection network (OMIN) promises high bandwidth, bandwidth density, and energy efficiency, and can potentially alleviate the memory wall problem. In this paper, we propose an optical inter/intra-chip processor-memory communication architecture, called MOCA. Experimental results and analysis show that MOCA can significantly improve system performance and energy efficiency. For example, comparing to Hybrid Memory Cube (HMC), MOCA can speedup application execution time by 2.6x, reduce communication latency by 75%, and improve energy efficiency by 3.4x for 256-core processors in 7 nm technology.

引用

页数：6

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