A 10-b Two-Stage DAC with an Area-Efficient Multiple-Output Voltage Selector and a Linearity-Enhanced DAC-Embedded Op-Amp for LCD Column Driver ICs

被引：38

作者：

Lu, Chih-Wen ^{[1
]}

Hsiao, Ching-Min ^{[2
]}

Yin, Ping-Yeh ^{[2
]}

机构：

[1] Natl Tsing Hua Univ, Dept Engn & Syst Sci, Hsinchu 30013, Taiwan

[2] Natl Chi Nan Univ, Dept Elect Engn, Puli 54561, Taiwan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2013年 / 48卷 / 06期

关键词：

Buffer amplifier; column driver; digital-to-analog converter (DAC); liquid crystal driver (LCD); LCD driver; op-amp; resistor-string DAC (RDAC); voltage selector; CLASS-B BUFFER; LOW-POWER; OPERATIONAL-AMPLIFIER; ARCHITECTURE;

D O I：

10.1109/JSSC.2013.2252525

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work proposes a 10-b two-stage DAC with an area-efficient multiple-output voltage selector and a linearity-enhanced DAC-embedded op-amp for LCD column driver ICs. The proposed voltage selector is divided into two stages, MSB and LSB decoders; this design requires fewer switches compared with tree-type voltage selectors, enabling a smaller die area. The proposed 6-b two-voltage selector occupies only 61% of the area needed for a 6-b tree-type two-voltage selector. This study also develops a generalized architecture for an area-efficient voltage selector for multiple outputs. To improve the linearity of the DAC-embedded op-amp, the differential pairs operate at the edge of the saturation region. The 10-b DAC prototypes were produced with 0.35-mu m/0.5-mu m CMOS technology with the worst DNL/INL being 0.44/0.58 LSB.

引用

页码：1475 / 1486

页数：12

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