Using FPGA-SoC Interface for Low Cost IoT Based Image Processing

被引:0
作者
Dhote, Shivank [1 ]
Charjan, Pranav [1 ]
Phansekar, Aditya [1 ]
Hegde, Aniket [1 ]
Joshi, Sangeeta [1 ]
Joshi, Jonathan [2 ]
机构
[1] Vidyalankar Inst Technol, Bombay, Maharashtra, India
[2] Eduvance, Bombay, Maharashtra, India
来源
2016 INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, COMMUNICATIONS AND INFORMATICS (ICACCI) | 2016年
关键词
FPGA; Image Processing; System on Chip; Internet of Things;
D O I
暂无
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
Multifunction image processing systems are typically deployed at the application site, but with the advent of Internet of Things(IoT) the design of such systems that are accessible remotely by applications over the internet is the need of the hour. These systems, being designed for data heavy applications need to possess a novel architecture design for image filtering and processing. This paper presents a multi-function image processing system that is accessible over the internet and is prototyped using a System on Chip (SoC) and FPGA interface. A pipelined based approach, inspired by a shift register based Random Access Memory design has been implemented for on-the-fly computation and minimal use of on-chip resources. The realization of the system was done using a low cost Spartan 6 FPGA and a Raspberry-pi B+ representing the ARM cortex based SoC. Data transfer between the FPGA and SoC has been achieved using a UART protocol. Computation time of different frame sizes for the system and standard I.P. software tools have been documented. Chip utilization and delays have also been reported.
引用
收藏
页码:1963 / 1968
页数:6
相关论文
共 11 条
[1]  
Bosi B., 1999, IEEE T VLSI SYSTEMS, V7
[2]  
Dally W., 1992, IEEE T PARALL DISTR, V3, P60
[3]  
Gonzalez R.C., 2005, Digital image processing
[4]  
Jinalkumar D, 2015, P IEEE ICACCI 2015, P533
[5]  
Joshi, 2006, P 49 IEEE MWCAS 2006, P475
[6]  
Joshi, 2007, P IEEE MWSCAS 2007, P1257
[7]  
Mai K, 2000, PROCEEDING OF THE 27TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, P161, DOI [10.1109/ISCA.2000.854387, 10.1145/342001.339673]
[8]  
Shivank D, 2015, IJCA P ICCT 2015, P11
[9]  
Singh G., 2005, P IEEE VLSI DES TEST, P151
[10]  
Trimberger S. M, 1995, FIELD PROGRAMMABLE G