Characterization of Fast Relaxation During BTI Stress in Conventional and Advanced CMOS Devices With HfO2/TiN Gate Stacks

We evaluate the performance of a novel fast characterization methodology for NBTI and PBTI measurements. We show that the use of a programmable PCI card in combination with linear current amplifiers provides the following means: a) to perform short BTI stresses down to similar to 30 mu s; (b) to perform fast sensing with delay times t(delay) similar to 30 mu s and a voltage resolution of similar to 1 mV; and (c) to use arbitrary programmable stress-and-sense sequences covering many decades in time. We used the fast PCI card-based measurement system for fast NBTI-relaxation measurements in SiON/poly-Si gate stacks, as well as for a systematic study of PBTI relaxation with HfO2/TiN gate stacks. We show for the first time that the V-t relaxation after PBT stress in nFETS with HfO2/TiN gate stacks and the V-t, relaxation after NBT stress in pFETs with SiON/poly-Si gate stacks exhibit strong similarities: We found the time dependence of both types of relaxation to exhibit to first order a log(t) dependence over seven orders of magnitude in time, suggesting that both phenomena are governed by charge removal by tunneling and that tunneling front-based modeling may be used to quantify the observations.