Hardware Reduction in Digital Delta-Sigma Modulators via Bus-Splitting and Error Masking-Part II: Non-Constant Input

被引：7

作者：

Fitzgibbon, Brian ^{[1
,2
]}

Kennedy, Michael Peter ^{[1
,2
]}

Maloberti, Franco ^{[3
]}

机构：

[1] Natl Univ Ireland Univ Coll Cork, Dept Elect & Elect Engn, Undergrad Elect Lab, Cork, Ireland

[2] Natl Univ Ireland Univ Coll Cork, Tyndall Natl Inst, Cork, Ireland

[3] Univ Pavia, Dept Elect, I-27100 Pavia, Italy

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2012年 / 59卷 / 09期

基金：

爱尔兰科学基金会;

关键词：

Bus-splitting; digital delta-sigma modulator (DDSM); nesting; AUDIO DAC; CONVERTERS;

D O I：

10.1109/TCSI.2012.2185278

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this two-part paper, a design methodology for hardware reduction in digital delta-sigma modulators (DDSMs) based on bus-splitting and error masking is presented. Part I addresses Multi stAge noise SHaping (MASH) DDSMs with constant inputs; Part II focuses on error feedback modulators (EFMs) with time-varying inputs. In this paper, we address EFMs with DC inputs plus additive input least significant bit (LSB) dithering and show how hardware reduction can be achieved with minimal degradation of the output spectrum. We also address EFMs with sinusoidal inputs and show how bus-splitting and error masking techniques can be used to obtain a trade-off between the modulator complexity and the achievable signal-to-noise ratio.

引用

页码：1980 / 1991

页数：12

共 22 条

[1] A low-power 98-dB multibit audio DAC in a standard 3.3-V 0.35-μm CMOS technology [J].

Annovazzi, M ;

Colonna, V ;

Gandolfi, G ;

Stefani, F ;

Baschirotto, A .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (07) :825-834

[2] A 0.22-mm2 7.25-mW per-channel audio stereo-DAC with 97-dB DR and 39-dB SNRout [J].

Colonna, V ;

Annovazzi, M ;

Boarin, G ;

Gandolfi, G ;

Stefani, F ;

Baschirotto, A .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (07) :1491-1498

[3] A 14-bit, 10-Msamples/s D/A converter using multibit ΣΔ modulation [J].

Falakshahi, K ;

Yang, CKK ;

Wooley, BA .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (05) :607-615

[4]

Fitzgibbon B., 2011, P INT WORKSH ADC MOD, P120

[5]

Fitzgibbon B, 2011, IEEE INT SYMP CIRC S, P1363, DOI 10.1109/ISCAS.2011.5937825

[6] Hardware Reduction in Digital Delta-Sigma Modulators Via Bus-Splitting and Error Masking-Part I: Constant Input [J].

Fitzgibbon, Brian ;

Kennedy, Michael Peter ;

Maloberti, Franco .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2011, 58 (09) :2137-2148

[7] A multibit delta-sigma audio DAC with 120-dB dynamic range [J].

Fujimori, I ;

Nogi, A ;

Sugimoto, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (08) :1066-1073

[8] Maximum sequence length MASH digital delta-sigma modulators [J].

Hosseini, Kaveh ;

Kennedy, Michael Peter .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2007, 54 (12) :2628-2638

[9] Prediction of the Spectrum of a Digital Delta-Sigma Modulator Followed by a Polynomial Nonlinearity [J].

Hosseini, Kaveh ;

Kennedy, Michael Peter ;

Lewis, Stephen H. ;

Levy, Bernard C. .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2010, 57 (08) :1905-1913

[10] Stable high-order delta-sigma digital-to-analog converters [J].

Kiss, P ;

Arias, J ;

Li, DD ;

Boccuzzi, V .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2004, 51 (01) :200-205

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