AIM technology for non-volatile memories microelectronics devices

被引:6
|
作者
Rigolli, Pier Luigi [1 ]
Rozzoni, Laura [1 ]
Turco, Catia [1 ]
Iessi, Umberto [1 ]
Polli, Marco [2 ]
Kassel, Elyakim [3 ]
Izikson, Pavel [3 ]
Avrahamov, Yosef [3 ]
机构
[1] STMicroelectronics Srl, Via C Olivetti 2, I-20041 Agrate Brianza, MI, Italy
[2] KLA Tencor, I-20063 Cernusco Sul Naviglio, MI, Italy
[3] KLA Tencor, IL-23100 Migdal Haemeq, Israel
来源
METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XX, PTS 1 AND 2 | 2006年 / 6152卷
关键词
overlay metrology; copper; CMP; archer AIM;
D O I
10.1117/12.656485
中图分类号
TH7 [仪器、仪表];
学科分类号
0804 ; 080401 ; 081102 ;
摘要
Accurate and precise overlay metrology is a critical requirement in order to achieve high product yield in microelectronic manufacturing. Meeting the tighter overlay measurement error requirements for 90 nm technology and beyond is a dramatic challenge for optical metrology techniques using only conventional overlay marks like Bar in Bar (BiB) or Frame in Frames (FiF). New deficiencies, affecting traditional overlay marks, become evident as microlithography processes are developed for each new design rule node. The most serious problems are total measurement uncertainty, CMP process robustness, and device correlation. In this paper we will review the superior performances of grating-based AIM marks to provide a complete solution to control lithography overlay errors for new generation devices. Examples of successful application of AIM technology to FEOL and Cu-BEOL process steps of advanced non volatile memory devices manufacturing are illustrated. An additional advantage of the adoption of AIM marks is that the significant reduction of target noise versus conventional marks revealed systematic differences within the lithography cluster which were previously obscure offering a new tool to optimize litho cells. In this paper we demonstrated that AIM target architecture enables high performance metrology with design rule segmented targets - a prerequisite to have overlay marks fully compatible with design rule sensitive process steps.
引用
收藏
页数:13
相关论文
共 50 条
  • [11] Carbon nanomaterials for non-volatile memories
    Ahn, Ethan C.
    Wong, H. -S. Philip
    Pop, Eric
    NATURE REVIEWS MATERIALS, 2018, 3 (03):
  • [12] Magnetic nanostructures for non-volatile memories
    Soltys, J.
    Gazi, S.
    Fedor, J.
    Tobik, J.
    Precner, M.
    Cambel, V.
    MICROELECTRONIC ENGINEERING, 2013, 110 : 474 - 478
  • [13] Raising the bar in non-volatile memories?
    Mehta, Rupal
    MATERIALS WORLD, 2009, 17 (09) : 8 - 8
  • [14] Gray counters for non-volatile memories
    Kulandai, Arockia David Roy
    Rose, John
    Schwarz, Thomas
    Memories - Materials, Devices, Circuits and Systems, 2022, 2
  • [15] Channel Coding Methods for Non-Volatile Memories
    Dolecek, Lara
    Sala, Frederic
    FOUNDATIONS AND TRENDS IN COMMUNICATIONS AND INFORMATION THEORY, 2016, 13 (01): : 2 - +
  • [16] Chalcogenide materials and their application to Non-Volatile Memories
    Sousa, Veronique
    MICROELECTRONIC ENGINEERING, 2011, 88 (05) : 807 - 813
  • [17] Test and Reliability of Emerging Non-Volatile Memories
    Hamdioui, Said
    Pouyan, Peyman
    Li, Huawei
    Wang, Ying
    Raychowdhur, Arijit
    Yoon, Insik
    2017 IEEE 26TH ASIAN TEST SYMPOSIUM (ATS), 2017, : 170 - 178
  • [18] Overview of emerging semiconductor non-volatile memories
    Fujisaki, Yoshihisa
    IEICE ELECTRONICS EXPRESS, 2012, 9 (10): : 908 - 925
  • [19] Investigating Fairness in Disaggregated Non-Volatile Memories
    Kommareddy, Vamsee Reddy
    Hughes, Clayton
    Hammond, Simon David
    Awad, Amro
    2019 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2019), 2019, : 104 - 110
  • [20] Overview and outlook of emerging non-volatile memories
    Mengwei Si
    Huai-Yu Cheng
    Takashi Ando
    Guohan Hu
    Peide D. Ye
    MRS Bulletin, 2021, 46 : 946 - 958