Comparison of contact resistance between accumulation-mode and inversion-mode multigate FETs

被引：17

作者：

Lee, Chi-Woo ^{[1
]}

Lederer, Dimitri ^{[1
]}

Afzalian, Aryan ^{[1
]}

Yan, Ran ^{[1
]}

Dehdashti, Nima ^{[1
]}

Xiong, Weize ^{[2
]}

Colinge, Jean-Pierre ^{[1
]}

机构：

[1] Tyndall Natl Inst, Cork, Ireland

[2] Texas Instruments Inc, SiTD, Dallas, TX USA

来源：

SOLID-STATE ELECTRONICS | 2008年 / 52卷 / 11期

基金：

爱尔兰科学基金会;

关键词：

Accumulation-mode; Silicon-on-insulator; Multigate MOSFET;

D O I：

10.1016/j.sse.2008.09.006

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The performances of accumulation-mode and inversion-mode multigate FETs are compared. The influence of gate underlap on the electrical properties is analyzed. Both simulation results and experimental data show that in a device with gate underlap, accumulation-mode devices have a higher current drive, lower source and drain resistance and less process variability than inversion-mode FETs. (C) 2008 Elsevier Ltd. All rights reserved.

引用

页码：1815 / 1820

页数：6

共 15 条

[1] Abiko H, 1995, 1995 SYMPOSIUM ON VLSI TECHNOLOGY, P23, DOI 10.1109/VLSIT.1995.520841
[2] ALLIBERT F, 2001, P IEEE INT SOI C, P149
[3] High performance and highly reliable novel CMOS devices using accumulation mode multi-gate and fully depleted SOI MOSFETs
Cheng, W.
Teramoto, A.
Kuroda, R.
Hirayama, M.
Ohmi, T.
[J]. MICROELECTRONIC ENGINEERING, 2007, 84 (9-10) : 2105 - 2108
[4] Impact of improved high-performance Si(110)-oriented metal-oxide-semiconductor field-effect transistors using accumulation-mode fully depleted silicon-on-insulator devices
Cheng, Weitao
Teramoto, Akinobu
Hirayama, Masaki
Sugawa, Shigetoshi
Ohmi, Tadahiro
[J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2006, 45 (4B): : 3110 - 3116
[5] PERFORMANCE AND POTENTIAL OF ULTRATHIN ACCUMULATION-MODE SIMOX MOSFETS
FAYNOT, O
CRISTOLOVEANU, S
AUBERTONHERVE, AJ
RAYNAUD, C
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1995, 42 (04) : 713 - 719
[6] Design optimization and performance projections of double-gate FinFETs with Gate-Source/Drain underlap for SRAM application
Kim, Seung-Hwan
Fossum, Jerry G.
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (08) : 1934 - 1942
[7] Kranti A, 2007, IEEE INT SOI CONF, P29
[8] Demonstration and analysis of accumulation-mode double-gate metal-oxide-semiconductor field-effect transistor
Masahara, Meishoku
Endo, Kazuhiko
Liu, Yongxun
Matsukawa, Takashi
O'uchi, Shinichi
Ishii, Kenichi
Sugimata, Etsuro
Suzuki, Eiichi
[J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2006, 45 (4B): : 3079 - 3083
[9] Park JW, 2003, 2003 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, P65
[10] RASHMI KA, 2008, P 4 EUROSOI WORKSH, P23

← 1 2 →