A strategy for long data retention time of 512Mb DRAM with 0.12μm design rule

被引：9

作者：

Uh, HS ^{[1
]}

Lee, JK ^{[1
]}

Lee, SH ^{[1
]}

Ahn, YS ^{[1
]}

Lee, HO ^{[1
]}

Hong, SH ^{[1
]}

Lee, JW ^{[1
]}

Koh, GH ^{[1
]}

Jeong, GT ^{[1
]}

Chung, TY ^{[1
]}

Kim, K ^{[1
]}

机构：

[1] Samsung Elect Co, Semicond R&D Ctr, Technol Dev Team, Yongin 449900, Kyunggi Do, South Korea

来源：

2001 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2001年

关键词：

D O I：

10.1109/VLSIT.2001.934930

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Data retention time has been investigated for the mass-productive 512Mb DRAM with 0.12mum design rule. Cell junction leakage components were for the first time analyzed by using test structure. It was found that process-induced trap density and electric field at the storage node(SN) junction should be reduced to control leakage current and thus data retention time. Moreover, we propose a novel cell transistor using Localized Channel and Field Implantation(LOCFI) which greatly suppresses the ion implantation damage and reduces the electric field at the same time. Finally, data retention time has been improved by 3similar to4 times due to the LOCFI cell transistor with optimized process conditions.

引用

页码：27 / 28

页数：2

共 2 条

[1] A 0.13 μm DRAM technology for giga bit density stand-alone and embedded DRAMs
Kim, KN
Chung, TY
Jeong, HS
Moon, JT
Park, YW
Jeong, GT
Lee, KH
Koh, GH
Shin, DW
Hwang, YS
Kwak, DW
Uh, HS
Ha, DW
Lee, JW
Shin, SH
Lee, MH
Chun, YS
Lee, JK
Park, BJ
Oh, JH
Lee, JG
Lee, SH
[J]. 2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, : 10 - 11
[2] Scaling guideline of DRAM memory cells for maintaining the retention time
Ueno, S
Inoue, Y
Inuishi, M
[J]. 2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, : 84 - 85

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