Architectures, stability and optimization for clock distribution networks

被引:2
作者
Carareto, Rodrigo [1 ]
Orsatti, Fernando M. [1 ]
Piqueira, Jose Roberto C. [1 ]
机构
[1] Univ Sao Paulo, Escola Politecn, BR-05508900 Sao Paulo, Brazil
关键词
Phase-locked loops; Synchronism quality; Tracking time; Voltage-control oscillator; DOUBLE-FREQUENCY JITTER; SYNCHRONIZATION; RECOGNITION;
D O I
10.1016/j.cnsns.2011.08.018
中图分类号
O29 [应用数学];
学科分类号
070104 ;
摘要
Synchronous telecommunication networks, distributed control systems and integrated circuits have its accuracy of operation dependent on the existence of a reliable time basis signal extracted from the line data stream and acquirable to each node. In this sense, the existence of a sub-network (inside the main network) dedicated to the distribution of the clock signals is crucially important. There are different solutions for the architecture of the time distribution sub-network and choosing one of them depends on cost, precision, reliability and operational security. In this work we expose: (i) the possible time distribution networks and their usual topologies and arrangements. (ii) How parameters of the network nodes can affect the reachability and stability of the synchronous state of a network. (iii) Optimizations methods for synchronous networks which can provide low cost architectures with operational precision, reliability and security. (C) 2011 Elsevier B. V. All rights reserved.
引用
收藏
页码:4672 / 4682
页数:11
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