A new method for the extraction of flat-band voltage and doping concentration in Tri-gate Junctionless Transistors

被引：8

作者：

Jeon, D. -Y. ^{[1
,3
]}

Park, S. J. ^{[1
,3
]}

Mouis, M. ^{[1
]}

Barraud, S. ^{[2
]}

Kim, G. -T. ^{[3
]}

Ghibaudo, G. ^{[1
]}

机构：

[1] Minatec, Grenoble INP, IMEP LAHC, F-38016 Grenoble, France

[2] CEA LETI Minatec, F-38054 Grenoble, France

[3] Korea Univ, Sch Elect Engn, Seoul 136701, South Korea

来源：

SOLID-STATE ELECTRONICS | 2013年 / 81卷

基金：

新加坡国家研究基金会;

关键词：

Junctionless Transistors (JLTs); Extraction method; Flat-band voltage (V-fb); Doping concentration (N-d); Effective width (W-eff); 2D numerical simulation; Sidewall accumulation current (I-d_side); NANOWIRE TRANSISTORS;

D O I：

10.1016/j.sse.2012.11.011

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new method for the extraction of flat-band voltage (V-fb) and channel doping concentration (N-d) in Tri-gate Junctionless Transistors (JLTs) is presented. The new method, based on the relationship between the top-effective width (W-top_eff) in accumulation and the effective width (Weir) in partial depletion, enables the extraction of V-fb, and Nd of JLT devices (here as approximate to 0.61 V and approximate to 6.4 x 10(18) cm(-3), respectively). The validity of the new method is also proved by 2D numerical simulations. Furthermore, it is emphasized that the sidewall accumulation current (I-d_side) behavior of Tri-gate JLT devices is found to decrease dramatically near Vfb, allowing an estimation of the V-fb position of JLT devices. (C) 2013 Elsevier Ltd. All rights reserved.

引用

页码：113 / 118

页数：6

共 11 条

[1] [Anonymous], P EUROSOI 2012
[2] DC and low frequency noise characterization of FinFET devices
Bennamane, K.
Boutchacha, T.
Ghibaudo, G.
Mouis, M.
Collaert, N.
[J]. SOLID-STATE ELECTRONICS, 2009, 53 (12) : 1263 - 1267
[3] Colinge JP, 2010, NAT NANOTECHNOL, V5, P225, DOI [10.1038/nnano.2010.15, 10.1038/NNANO.2010.15]
[4] Doyle B., 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407), P133, DOI 10.1109/VLSIT.2003.1221121
[5] Evaluation of variability performance of junctionless and conventional Trigate transistors
Ghibaudo, G.
[J]. SOLID-STATE ELECTRONICS, 2012, 75 : 13 - 15
[6] Analysis of Threshold Voltage Variability Due to Random Dopant Fluctuations in Junctionless FETs
Gnudi, A.
Reggiani, S.
Gnani, E.
Baccarani, G.
[J]. IEEE ELECTRON DEVICE LETTERS, 2012, 33 (03) : 336 - 338
[7] ELECTRONIC DEVICES Nanowire transistors made easy
Ionescu, Adrian M.
[J]. NATURE NANOTECHNOLOGY, 2010, 5 (03) : 178 - 179
[8] Direct measurement of top and sidewall interface trap density in SOI FinFETs
Kapila, G.
Kaczer, B.
Nackaerts, A.
Collaert, N.
Groeseneken, G. V.
[J]. IEEE ELECTRON DEVICE LETTERS, 2007, 28 (03) : 232 - 234
[9] Mobility analysis of surface roughness scattering in FinFET devices
Lee, Jae Woo
Jang, Doyoung
Mouis, Mireille
Kim, Gyu Tae
Chiarella, Thomas
Hoffmann, Thomas
Ghibaudo, Gerard
[J]. SOLID-STATE ELECTRONICS, 2011, 62 (01) : 195 - 201
[10] Variability Impact of Random Dopant Fluctuation on Nanoscale Junctionless FinFETs
Leung, Greg
Chui, Chi On
[J]. IEEE ELECTRON DEVICE LETTERS, 2012, 33 (06) : 767 - 769

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