A new method for the extraction of flat-band voltage and doping concentration in Tri-gate Junctionless Transistors

被引:8
作者
Jeon, D. -Y. [1 ,3 ]
Park, S. J. [1 ,3 ]
Mouis, M. [1 ]
Barraud, S. [2 ]
Kim, G. -T. [3 ]
Ghibaudo, G. [1 ]
机构
[1] Minatec, Grenoble INP, IMEP LAHC, F-38016 Grenoble, France
[2] CEA LETI Minatec, F-38054 Grenoble, France
[3] Korea Univ, Sch Elect Engn, Seoul 136701, South Korea
基金
新加坡国家研究基金会;
关键词
Junctionless Transistors (JLTs); Extraction method; Flat-band voltage (V-fb); Doping concentration (N-d); Effective width (W-eff); 2D numerical simulation; Sidewall accumulation current (I-d_side); NANOWIRE TRANSISTORS;
D O I
10.1016/j.sse.2012.11.011
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A new method for the extraction of flat-band voltage (V-fb) and channel doping concentration (N-d) in Tri-gate Junctionless Transistors (JLTs) is presented. The new method, based on the relationship between the top-effective width (W-top_eff) in accumulation and the effective width (Weir) in partial depletion, enables the extraction of V-fb, and Nd of JLT devices (here as approximate to 0.61 V and approximate to 6.4 x 10(18) cm(-3), respectively). The validity of the new method is also proved by 2D numerical simulations. Furthermore, it is emphasized that the sidewall accumulation current (I-d_side) behavior of Tri-gate JLT devices is found to decrease dramatically near Vfb, allowing an estimation of the V-fb position of JLT devices. (C) 2013 Elsevier Ltd. All rights reserved.
引用
收藏
页码:113 / 118
页数:6
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