A multi-radix FFT processor using Pipeline in Memory-based Architecture (PIMA) for DVB-T/H systems

Digital Video Broadcasting-Terrestrial/Handheld (DV-B-T/H) systems require a core computation of 2K/4K/8K-point Fast Fourier Transformation (FFT). The major design challenge is that the length of the FFT is not only long but also variable. There are only very few works discussing long length FFT design, and almost none of them has discussed the solutions for the difficulty of variable length computation. To solve this design challenge, this work presents a multi-radix FFT using Pipeline in Memory-based Architecture (PIMA). The proposed PIMA FFT processor combines both the merits of pipeline architectures and those of memory-based architectures. Thus, this work possesses the features of high data throughput rate and high flexibility without incurring the issue of high memory access. This work has been designed and verified thoroughly following the VLSI design flow. After implemented using the 1P6M TSMC 0.18-mu m CMOS technology, this work can meet the FFT performance requirements of DVB-T/H with 5 MHz frequency.