Novel 7T SRAM cell for low power cache design

被引：0

作者：

Aly, RE ^{[1
]}

Faisal, MI ^{[1
]}

Bayoumi, MA ^{[1
]}

机构：

[1] Univ Louisiana, Ctr Adv Comp Studies, Lafayette, LA 70504 USA

来源：

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Low-power on-chip cache is a crucial part in many applications. Conventional write operation depends on discharging/charging large bit lines capacitance which causes high power consumption. We propose a novel 7T SRAM cell that only depends on one of the bit lines during a write operation and reduce the write power consumption. HSPICE simulation shows that at least 49% write power saving, higher stability, and no performance degradation with additional 12.25% silicon area.

引用

页码：171 / 174

页数：4

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