A technique for modular design of self-checking carry-select adder

被引:11
作者
Vasudevan, DP [1 ]
Lala, PK [1 ]
机构
[1] Univ Arkansas, Dept Comp Sci & Comp Engn, Fayetteville, AR 72701 USA
来源
DFT 2005: 20TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS | 2005年
关键词
D O I
10.1109/DFTVS.2005.15
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The carry-select adders provide significant speed improvement over other types of adders. This paper proposes a new approach for constructing self-checking carry-select adders of arbitrary size. The scheme is illustrated with the implementation of a 2-bit carry select adder that can detect a pre-determined set of faults online. Adders of arbitrary size can be constructed by simply cascading the appropriate number of 2-bit adders. A range of adders from 4 bit to 128 bits was designed using this approach employing a 0. 5 mu CMOS technology. The area needed for implementing the self-checking adders is 16.07 % to 20.67% more than that required in adders without built-in self-checking capability.
引用
收藏
页码:325 / 333
页数:9
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