Aging Precursor Identification and Lifetime Estimation for Thermally Aged Discrete Package Silicon Power Switches

Thermal/power cycles are widely acknowledged methods to accelerate the package related failures. Many studies have focused on one particular aging precursor at a time and continuously monitored it using custom-built circuits. Due to the difficulties in taking sensitive measurements, the reported findings are more on the quantities requiring less sensitive measurements. In this paper, two custom-designed testbeds are used to age a number of power MOSFETs and insulated gate bipolar transistors. An automated curve tracer is utilized to capture parametric variations in I-V curves, parasitic capacitances, and gate charges at certain time intervals. The results suggest that the only viable aging precursors are the on-state voltage drop/on-state resistance, body diode voltage drop, parasitic capacitances, and gate threshold voltage for die attach solder and gate-oxide degradation mechanisms. Based on the experimental results, gate threshold voltage variation is empirically modeled to estimate the remaining useful lifetime of the switches experiencing gate oxide degradation. The model parameters are found by the least squares method applied to inliers determined by the random sample and consensus outlier removal algorithm.