An innovative low-density parity-check code design with near-Shannon-limit performance and simple implementation

被引：25

作者：

Eroz, M ^{[1
]}

Sun, FW ^{[1
]}

Lee, LN ^{[1
]}

机构：

[1] Hughes Netowrk Syst, Germantown, MD 20876 USA

来源：

IEEE TRANSACTIONS ON COMMUNICATIONS | 2006年 / 54卷 / 01期

关键词：

digital video broadcasting (DVB); high-order modulation; iterative decoding; low-density parity-check (LDPC) codes; very-large-scale integration (VLSI) implementation;

D O I：

10.1109/TCOMM.2005.861681

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel parity-check matrix design for low-density parity-check (C) codes is described. By eliminating the routing problem associated with LDPC codes, the design results in a small implementation area, and the codes have outstanding error-rate performance close to the Shannon limit for a wide range of code rates, from 1/4 to 9/10, and for various modulation schemes such as binary phase-shift keying (PSK), quaternary PSK, 8-PSK, 16-amplitude PSK (APSK), and 32-APSK. As a result, LDPC codes designed with this method have been standardized for next-generation digital video broadcasting.

引用

页码：13 / 17

页数：5

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