Design of a lower-error fixed-width multiplier for speech processing application

被引：0

作者：

Van, LD ^{[1
]}

Wang, SS ^{[1
]}

Shing, TC ^{[1
]}

Feng, VS ^{[1
]}

Jeng, BS ^{[1
]}

机构：

[1] Natl Taiwan Univ, Dept Elect Engn, Lab 353, Taipei 10764, Taiwan

来源：

ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 3: ANALOG AND DIGITAL SIGNAL PROCESSING | 1999年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A lower-error and lower-variance n X n multiplier is suitably proposed for VLSI design. Considering next lower significant stage in Pn-1 column and useful error-compensation model in the least significant part, and utilizing a near optimized index to classify the error terms are our strategies in order to achieve lower error and variance as compared with previously proposed structure in the subproduct-array of Baugh-Wooley algorithm. This novel structure applied to the fixed-width lowpass digital FIR filter for speech signal processing system has excellent performance in reducing maximum error, average error, and variation of errors as shown in given tables and figures.

引用

页码：130 / 133

页数：4