A Type-3 PLL for Single-Phase Applications

被引:27
|
作者
Bamigbade, Abdullahi [1 ]
Khadkikar, Vinod [1 ]
Hosani, Mohamed Al [2 ]
机构
[1] Khalifa Univ, Adv Power & Energy Ctr, Elect Engn & Comp Sci Dept, Abu Dhabi 127788, U Arab Emirates
[2] Abu Dhabi Distribut Co, Demand Side Management Dept, Abu Dhabi 219, U Arab Emirates
关键词
Phase locked loops; Stability analysis; Steady-state; Power system stability; Transfer functions; Frequency estimation; Dynamic performance; gain margin (GM); loop filter (LF); phase-locked loop (PLL); phase margin; stability; steady-state error; FREQUENCY-LOCKED LOOP; SYNCHRONIZATION; PERFORMANCE; TIME;
D O I
10.1109/TIA.2020.2999435
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
This article proposes an effective solution by means of gain and phase-lead compensations to overcome the challenges of instability and slow dynamic performance exhibited by single-phase type-3 phase-locked loops (PLLs). By considering a single-phase second-order generalized integrator based type-3 PLL, a detailed design guideline is provided in choosing the PLL's parameters. Stability analysis of the designed PLL reveals that its finite gain margin causes PLL instability under severe voltage dip, while its limited phase margin results in poor dynamics. Therefore, gain compensation is carried out within a limited region such that the PLL's stability limit is not exceeded, while phase-lead compensation is employed to enhance the PLL's damping. When both modifications are incorporated within the PLL loop, the PLL's speed of estimation is improved significantly when compared with those of existing solutions applied to type-3 PLLs and the response obtained is comparable to that of a type-2 PLL. The performance evaluation of the proposed solution is carried out by experimental comparison with a standard single-phase type-3 PLL, a type-3 PLL with the amplitude normalization system, a phase feed-forward type-3 PLL, a dual-loop type-3 PLL, and a type-2 PLL.
引用
收藏
页码:5533 / 5542
页数:10
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