Capacitance extraction for the nano-scale on-chip interconnects

被引：0

作者：

Goel, AK ^{[1
]}

Gopinathannair, H ^{[1
]}

机构：

[1] Michigan Technol Univ, Dept Elect & Comp Engn, Houghton, MI 49931 USA

来源：

2004 IEEE International Conference on Semiconductor Electronics, Proceedings | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Single-level and multi-path interconnect structures embedded in dielectrics on a silicon substrate are designed for simulation and capacitance extractions for these nano-scale three dimensional structures are done using the SILVACOO TCAD tools. Simulation results are used to study the dependences of the ground and coupling capacitances on the permittivity of the dielectric material used and the thickness of the overlapping dielectric in addition to the geometry of the interconnect structure.

引用

页码：112 / 116

页数：5

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